In recent years, research and development are conducted on a nonvolatile memory device (hereinafter also referred to as a “variable resistance nonvolatile memory device” or simply as a “nonvolatile memory device”) having memory cells including variable resistance elements. A variable resistance element is an element that has a property that a resistance value changes (changes between a high resistance state and a low resistance state) according to an electrical signal and enables information to be written through this change in resistance value.
Examples of a structure of memory cells including variable resistance elements include two types: 1T1R structure and cross point structure. In the 1T1R structure, memory cells each of which includes one variable resistance element and one selection transistor for selecting the memory cell using a word line are connected between bit lines and source lines arranged to cross each other. On the other hand, in the cross point structure, each memory cell is placed at a different one of cross points of bit lines and word lines arranged to cross each other, so as to be provided between a bit line and a word line. Various types of such variable resistance nonvolatile memory devices are developed in recent years (see Patent Literatures (PTLs) 1 to 3, for instance).
PTL 1 discloses a nonvolatile memory device including memory cells having the 1T1R structure. In PTL 1, drive positions of a bit line and a source line are placed at opposite sides across a memory cell array with a view to reducing a variation in memory cell current (i.e., current flowing through a memory cell) at a time of reading regardless of a position of a selected memory cell, and achieving stable reading. In addition, PTL 1 discloses that the both lines are formed in the same layer and the same shape and of the same material to have the same sheet resistance, thereby keeping constant a sum of resistances of the source line and the bit line in a path of a memory cell current regardless of a position of a memory cell and achieving the stable reading.
PTL 2 discloses a nonvolatile memory device including memory cells having the cross point structure, and has an object to remove an influence of a voltage drop caused by a wiring resistance (i.e., parasitic resistance) of a word line and a bit line on each memory cell, and to ensure a write operation margin and a read operation margin. PTL 2 also discloses, as a structure of a power circuit that generates a bias in writing and reading, successfully compensating a voltage drop due to a difference in position between a far end and a near end from a drive circuit of a memory cell to be accessed, by setting a reference current value for determining an applied voltage value or a memory cell current to a memory cell so that the voltage drop caused by the wiring resistance is compensated for each position of word line drive circuits or bit line drive circuits to be activated (i.e., selected) based on an address of a selected memory cell.
PTL 3 discloses a technique of increasing, for an upper layer, a channel width of a drive circuit that drives bit lines and word lines, so as to reduce a voltage drop of upper-layer memory cells caused by resistance of vias for connecting bit lines and word lines, and to minimize an increase of a drive circuit region in a nonvolatile memory device including memory cells having a multilayer cross point structure.
According to PTLs 1 to 3 described above, it is possible to reduce characteristic variation of memory cells at a time of writing, by offsetting dependency of characteristics and operation of a nonvolatile memory device on positions of the memory cells. (Hereinafter the dependency is also referred to as “memory cell position dependency.”)
In contrast, already proposed is a method of enhancing a parallel degree of writing and throughput by simultaneously writing bits on a selected source line or word line (hereinafter such writing is also referred to as “mufti-bit simultaneous writing”) so that writing whose speed is faster than existing flash memories is achieved by taking advantage of high-speed resistance change which is a feature of memory cells including variable resistance elements.